The present invention relates to a PLL (Phase Locked Loop) control circuit for digital oscillation frequency control and a control method adopted in the same.
In such communication units as heterodyne receivers, particularly portable telephone sets, a local oscillator executes a mixing operation to obtain an intermediate frequency signal having a fixed frequency difference from a desired received signal frequency. Also, the intermediate frequency signal thus obtained is amplified in a high grain intermediate frequency amplifier to realize high reception sensitivity. To this end, a PLL is often used as local oscillator.
FIG. 5 is a block diagram showing a prior art example of PLL control circuit, and FIG. 10 shows the frame timing of al usual digital portable telephone set. As shown in FIG. 10, in the digital portable telephone set a reception channel, peripheral channels and a transmission channel are switched one over to another in a fixed cycle. In this case, the PLL output frequency should also be switched.
In this case, the PLL output frequency should be pulled in a short period of time at the time of the frequency switching. The prior art PLL control circuit will now be described with reference to FIG. 5 by assuming PLL output frequency to be, for instance:
680 MHz at the reception channel time,
690 MHz at the peripheral channel time and
740 MHz at the transmission channel time.
The PLL circuit shown in FIG. 5 is a typical one comprising a reference frequency oscillator 101, a voltage controlled oscillator (VCO) 102, variable frequency dividers 104 and 105 for frequency dividing the outputs of the two oscillators 101 and 102, respectively, a phase comparator 108 for phase comparing the outputs of the two variable frequency dividers 104 and 105, a charge pump 107 connected to the output side of the phase comparator 106, and a low-pass filter 103 for filtering the output of the charge pump 107 and feeding back the filtered output to the VCO 102. The above component constitutes a typical PLL. The PLL control circuit further comprises a serial-to-parallel (S/P) converter 110 for controlling the variable frequency dividers 104 and 105, a parallel-to-serial (P/S) converter 111 for controlling the S/P converter 110, a timer circuit 112 and a central processing unit (CPU) 113. The individual circuit components noted above are well known to one skilled in the art, and they will not be described here.
The reference frequency of the reference frequency oscillator 101 is assumed to be 14.4 MHz. Then, when the output frequency of the VCO 102 is set to 680 MHZ at the reception channel time:
the phase comparison frequency of the phase comparator 106 is 200 kHz;
the frequency division number of the variable frequency divider 104 is 14.4 MHz/200 kHz=72; and
the frequency division number of the variable frequency divider 105 is 680 MHz/200 kHz=3,400.
When the output frequency of the VCO 102 is set to 690 MHz at the peripheral channel time:
the phase comparison frequency of the phase comparator 106 is 200 kHz;
the frequency division number of the variable frequency divider 104 is 14.4 MHz/200 kHz=72; and
the frequency division number of the variable frequency divider 105 is 690 MHZ/200 kHz=3.450.
When the output frequency of the VCO 102 is set to 740 MHz at the transmission channel time:
the phase comparison frequency of the phase comparator 106 is 160 MHz;
the frequency division number of the variable frequency divider 164 is 14.4 HMz/160 kHz=90; and
the frequency division raito of the variable frequency divider 104 is 740 MHz/160 kHz=4,625.
The operation in the case of sequentially designating the above settings in a time schedule as shown in FIG. 10, will now be described with reference to the flow chart of FIG. 7, i.e., the flow chart of control routine in the CPU 113 shown in FIG. 5. FIG. 6 shows the format of serial data. The serial data consist of data xe2x80x9cD00xe2x80x9d to xe2x80x9cD16xe2x80x9d, and designate the frequency division. number of the variable frequency dividers 104 and 105 in the form of binary numbers.
Referring to the flow chart of FIG. 7, in a step S1 the CPU 113 waits for an interruption from the timer circuit 112. When receiving an interruption from the timer circuit 112, the CPU determines the kind of the interruption. Specifically, in a step S2 the CPU checks whether the kind of the interruption is xe2x80x9cAxe2x80x9d. When the kind is xe2x80x9cAxe2x80x9d, the CPU executes steps S3 to S5. More specifically, when the kind is xe2x80x9cAxe2x80x9d, corresponding to the frequency setting at the reception channel time, the CPU sets the frequency division number of the variable frequency divider 104 by using the format of xe2x80x9cD00xe2x80x9d=xe2x80x9c0xe2x80x9d in FIG. 6 (step S3). Then, the CPU waits for completion of the serial output from the P/S converter 111 (step S4). Then, the CPU sets the frequency division number of the variable frequency divider 105 by using the format of xe2x80x9cD00xe2x80x9d=xe2x80x9c1xe2x80x9d in FIG. 6 (step S5).
When it is not determined in the step S2 that the kind of interruption is xe2x80x9cAxe2x80x9d, the CPU executes a step S6 of checking whether the kind of interruption is xe2x80x9cBxe2x80x9d. When it is determined in the step S6 that the kind of interruption is xe2x80x9cBxe2x80x9d, the CPU executes steps S7 to S9 for frequency setting at the peripheral channel time shown in FIG. 10. More specifically, in the step S7 the CPU sets the frequency division number of the variable frequency divider 104 by using the format of xe2x80x9cD00xe2x80x9d=xe2x80x9c0xe2x80x9d. Then, in the step S8 the CPU waits for completion of the serial output of the P/S converter 111. Then, in the step S9 the CPU sets the frequency division number for the variable frequency divider 105 by using the format of xe2x80x9cD00xe2x80x9d=xe2x80x9c1xe2x80x9d.
Finally, when it is not determined in the step S6 that the kind of interruption is xe2x80x9cBxe2x80x9d, the CPU executes step S10 to check whether the kind of interruption is xe2x80x9cCxe2x80x9d. When the kind is xe2x80x9cCxe2x80x9d, the CPU executes steps S11 to S13 for frequency setting at the transmission channel time shown in FIG. 10. More specifically, in the step S11 the CPU sets the frequency division number of the variable frequency divider 104 by using the format of xe2x80x9cD00xe2x80x9d=xe2x80x9c0xe2x80x9d. Then, in the step S12 the CPU waits for completion of the serial output of the P/S converter 111. Subsequently, in the step S13 the CPU sets the frequency division number for the variable frequency divider 105 by using the format of xe2x80x9cD00xe2x80x9d=xe2x80x9c1xe2x80x9d in FIG. 6.
Problems arising in the above prior art technique will now be described in connection with a case of frequency switching from the transmission channel to the reception channel.
At the transmission channel time, the frequency division number of the variable frequency divider 104 is set to 90, so that the output frequency thereof is 14.4 MHz/90=160 kHz. The frequency division number of the variable frequency divider 105 is set to 4,625, and the PLL is controlled to make the output frequency of the variable frequency divider 104 equal to the output frequency (160 kHz) of the variable frequency divider 104. The frequency of the VCO 102 is 160 kHZxc3x974,625=740 MHz.
For frequency switching to the reception channel frequency, the frequency division number of the variable frequency divider 104 is set to 72 so that the output frequency thereto is 14.4 MHz/72=200 kHz. At this time, the frequency division number of the variable frequency divider 105 remains at 4,625, and the PLL circuit is controlled such that its output frequency approaches 200 kHzxc3x974,625=925 MHz. Subsequently, the frequency division number of the variable frequency divider 105 is set to 3,400. At this time and only at this time the PLL circuit is controlled to make the output frequency of the VCO 102 to be 200 kHzxc3x973,400=68 MHz.
In the above process of switching the output frequency of the PLL: circuit, by switching the frequency from 740 MHz to 680 MHz, the frequency is switched from 740 MHz to 925 MHz and then to 680 MHz. It is thus a problem that a certain time is taken from the start of the frequency switching operation until the desired frequency is obtained.
Besides, as is: obvious from the flow chart of FIG. 7, the CPU 113 requires a complicated control, and its burden necessary for the output frequency switching of the PLL circuit is considerable.
FIG. 8 is a block diagram showing a different prior art example. FIG. 9 is a flow chart illustrating the operation of this example. FIG. 8 is similar to FIG. 5. Thus, like components are designated by like reference numerals, and only the difference of this example from the preceding example will be mainly described. The PLL control circuit shown in FIG. 8 uses a VCO 202 of frequency band switching type, which is capable of being frequency band switched by the CPU 113. Such VCO 202 is often employed in case where the oscillation frequency band is broad. In this case, after the output frequency setting of the variable frequency divider 105 a signal for switching the frequency band of the VCO 202 is provided from a port of the CPU 113.
The operation of the PLL circuit shown in FIG. 8 is as shown in the flow chart of FIG. 9. In the Figure, steps S20 to S24, S26 to S29 and S312 to S34 correspond to the steps S1 to S5, S6 to S9 and S10 to S13 in FIG. 7, respectively. This example is thus different in that when the kind of interruption is determined to be xe2x80x9cAxe2x80x9d, xe2x80x9cBxe2x80x9d and xe2x80x9cCxe2x80x9d, the steps S25, S30 and S35 of setting the control output of the VCO 202 are executed, respectively. To this end, the PLL circuit executes a pull-in operation after the frequency band switching of the VCO 202, thus giving rise to the problem that further time is taken until the frequency. is stabilized.
An object of the present invention is to provide a PLL control circuit, the output frequency of which is pulled in to a desired frequency in a relatively short period of time at the time of the frequency switching, and a method of controlling the same.
According to a first aspect of the present invention, there is provided a PLL control circuit comprising a reference frequency oscillator for executing oscillation at a reference oscillation frequency, a voltage controlled oscillator (VCO) for feeding out an output at a frequency corresponding to a control voltage, first and second variable frequency dividers for frequency dividing the outputs of the reference frequency oscillator and the VCO, respectively, a phase comparator for phase comparing the outputs of the two variable frequency dividers, a low-pass filter for filtering out the output of the phase comparator and feeding the control voltage to the VCO, wherein: the PLL control circuit further comprises at least one register for storing the frequency division numbers of the variable frequency dividers.
According to a second aspect of the present invention, there is provided a PLL control circuit comprising a reference frequency oscillator for executing oscillation at a reference oscillation frequency, a voltage controlled oscillator (VCO) for feeding out an output at a frequency corresponding to a control voltage, first and second variable frequency dividers for frequency dividing the outputs of the reference frequency oscillator and the VCO, respectively, a phase comparator for phase comparing the outputs of the two variable frequency dividers, a low-pass filter for filtering out the output of the phase comparator and feeding the control voltage to the VCO, wherein: the frequency division numbers of the variable frequency dividers are simultaneously set by the register.
According to a third aspect of the present invention, there is provided a PLL control circuit comprising a reference frequency oscillator for executing oscillation at a reference oscillation frequency, a voltage controlled oscillator (VCO) for feeding out an output at a frequency corresponding to a control voltage, first and second variable frequency dividers for frequency dividing the outputs of the reference frequency oscillator and the VCO, respectively, a phase comparator for phase comparing the outputs of the two variable frequency dividers, a low-pass filter for filtering out the output of the phase comparator and feeding the control voltage to the VCO, wherein: the PLL control circuit further comprises at least one register for storing the frequency division numbers of the variable frequency dividers and a timer circuit for determining the timing of switching of the frequency division numbers of the variable frequency dividers.
According to a fourth aspect of the present invention, there is provided a PLL control circuit comprising a reference frequency oscillator for executing oscillation at a reference oscillation frequency, a voltage controlled oscillator (VCO) for feeding out an output at a frequency corresponding to a control voltage, first and second variable frequency dividers for frequency dividing the outputs of the reference frequency oscillator and the VCO, respectively, a phase comparator for phase comparing the outputs of the two variable frequency dividers, a low-pass filter for filtering out the output of the phase comparator and feeding the control voltage to the VCO, wherein: the frequency division numbers of the variable frequency dividers are simultaneously set by the register and the PLL control circuit further comprises a timer circuit for determining the timing of switching of the frequency division numbers of the variable frequency dividers.
Two registers corresponding to the first and second variable frequency dividers are provided. A plurality of registers are provided for storing serial data for switching the frequency division numbers of the variable frequency dividers to different values. The timer circuit operates according to the output of the reference frequency oscillator of the PLL. The PLL control circuit further comprises a CPU controlled by the timer circuit, the timer circuit being capable of producing an interruption to the CPU after the reading of the contents stored in the registers for storing the serial data.
According to other aspect of the present invention, there is provided, in a PLL in which the outputs of variable frequency dividers for frequency dividing the outputs of a reference frequency divider and a VCO, respectively, are compared in a phase comparator, a PLL control method for switching the frequency division numbers of the variable frequency dividers to different values, wherein: the frequency division numbers of the variable frequency dividers are switched at the same time to sequentially different values by registers storing the frequency division numbers.